WikiChip

The official WikiChip FlipBoard profile. Hardware (logic), computer architectures, & semiconductor engineering. Technical.

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TSMC Details 5 nm
wikichip.org - David Schor
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with a …
March 21
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IBM
IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache
wikichip.org - David Schor
IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the …
March 8
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TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications
wikichip.org - David Schor
TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for …
March 3
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CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor
wikichip.org - David Schor
CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active …
March 1
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Intel Corporation
Intel Refreshes 2nd Gen Xeon Scalable, Slashes Prices
wikichip.org - David Schor
Intel refreshes its second-generation Xeon Scalable lineup mid-cycle with new mainstream dual-socket CPUs, improving the performance-per-dollar by as …
February 27
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Radeon RX 5700: Navi and the RDNA Architecture
wikichip.org - David Schor
A look at AMD's Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.
February 23
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7nm Boosted Zen 2 Capabilities but Doubled the Challenges
wikichip.org - David Schor
The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route …
February 21
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Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55
wikichip.org - David Schor
Arm launches two new IPs for deeply-embedded AI: the Cortex-M55 with the new M-Profile Vector Extension (Helium), and the Ethos-U55, an …
February 10
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Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect
wikichip.org - David Schor
A dive into the Rosetta ASIC switch, the engine behind Cray's new Slingshot interconnect powering the upcoming Shasta exascale supercomputers.
February 9
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Arm Ethos is for Ubiquitous AI At the Edge
wikichip.org - David Schor
Arm's Ethos family takes aim at ubiquitous AI with NPUs for ultra-low power IoT to high-performance smartphones and AR/VR.
February 6
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Intel Axes Nervana Just Two Months After Launch
wikichip.org - David Schor
Intel axes Nervana in favor of Habana.
February 3
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Centaur New x86 Server Processor Packs an AI Punch
wikichip.org - David Schor
Earlier last month we detailed Centaur’s latest CNS core which is part of their new CHA SoC. WikiChip had the opportunity to speak with the Centaur …
January 24
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ASML Q4: NXE:3400C Machines Ramp; Strong Growth Due to EUV in 2020
wikichip.org - David Schor
ASML saw a strong fourth-quarter in 2019 thanks to a large EUV shipment with the production of NXE:3400C machines ramping up. ASML shipped a total of …
January 22
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Ayar Labs Realizes Co-Packaged Silicon Photonics
wikichip.org - David Schor
Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the …
January 19
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TSMC Q4: 7nm Dominates Revenue, Preps 5nm Ramp, 6nm By EOY
wikichip.org - David Schor
7-nanometer contributes the lion's share of wafer revenue to TSMC's fourth-quarter driven by growth from smartphones and HPC. The company is also …
January 17
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A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC
wikichip.org - David Schor
A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.
January 12
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AMD Launches New Entry-Level Mobile ‘Dali’ Processors
wikichip.org - David Schor
AMD launches new value and entry-level mobile processors, codenamed Dali.
January 9
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OCP Bunch of Wires: A New Open Chiplets Interface For Organic Substrates
wikichip.org - David Schor
A look at a Bunch of Wires, a new open standard chiplets interconnect being proposed by the OCP ODSA group intended for standard organic multi-chip …
January 5
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OCP Makes a Push for an Open Chiplet Marketplace
wikichip.org - David Schor
Two major trends have been defining the future of silicon in the data center and edge for the coming decade. Specialized devices are becoming key to …
January 4
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Chuck Peddle: Personal Computer Pioneer, Dies At 82
wikichip.org - David Schor
Personal computer pioneer, Chuck Peddle, dies at 82.
Dec 24, 2019
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A Look At The Habana Inference And Training Neural Processors
wikichip.org - David Schor
A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.
Dec 15, 2019
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TSMC Digs Trenches In Search Of Higher Performance
wikichip.org - David Schor
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench …
Dec 14, 2019
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UMC Rolls Out 22-Nanometer
wikichip.org - David Schor
UMC says it has started rolling out its 22-nanometer planar process, offering a new lower-power and cost-sensitive migration path from existing 40nm …
Dec 13, 2019
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Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs
wikichip.org - David Schor
Zhaoxin unveiled plans for two new x86 SoC designs: a high-performance 16-nanometer server chip with up to 32 cores and a separate 7 nm mobile and …
Dec 12, 2019
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Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029
wikichip.org - David Schor
Intel's process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into 2029.
Dec 10, 2019
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7 Nanometer
Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029
wikichip.org - David Schor
This week IEEE is hosting its flagship process technology conference – IEDM. In a keynote by ASML’s CEO, Martin van den Brink outlined their vision …
Dec 11, 2019
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Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512
wikichip.org - David Schor
Centaur lifts the veil on CNS, its next-generation x86 core for data center and edge computing. The core improving performance in many areas and adds …
Dec 9, 2019
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Intel Starts Shipping Initial Nervana NNP Lineup
wikichip.org - David Schor
Intel starts shipping its initial Nervana NNP lineup for both inference and training acceleration with four initial models in three different form …
Dec 6, 2019
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NEC Refreshes SX-Aurora Vector Engine, Outlines Roadmap
wikichip.org - David Schor
NEC refreshes its SX-Aurora Vector Engine accelerator cards, adopts AMD processors, and outlines roadmap.
Nov 30, 2019
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Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip
wikichip.org - David Schor
Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS as well as a …
Nov 24, 2019