Van-Loi Le

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VHDL code for Seven-Segment Display on Basys 3 FPGA

Last time, I wrote a full FPGA tutorial on how to control the 4-digit 7-segment display on Basys 3 FPGA. A full Verilog code for displaying a …

[FPGA Tutorial] Seven-Segment LED Display on Basys 3 FPGA

This FPGA tutorial will guide you how to control the 4-digit seven-segment display on Basys 3 FPGA Board. A display controller will be designed in …

Full Verilog code for Moore FSM Sequence Detector

This Verilog project is to present a full Verilog code for Sequence Detector using Moore FSM. A Verilog Testbench for the Moore FSM sequence detector …

Car Parking System in VHDL

This VHDL project presents a car parking system in VHDL using Finite State Machine (FSM). VHDL code and testbench for the car parking system are …

VHDL code for single-port RAM

This VHDL post presents a VHDL code for a single-port RAM (Random Access Memory). The VHDL testbench code is also provided to test the single-port …

Verilog code for PWM generator

This Verilog project presents a Verilog code for PWM generator with Variable Duty Cycle. Last time, I presented a VHDL code for a PWM generator.<p>The …

VHDL code for Comparator

This VHDL project presents a simple VHDL code for a comparator which is designed and implemented in Verilog before. Full VHDL code together with test …

VHDL code for Traffic light controller

A VHDL code for a traffic light controller on FPGA is presented. The traffic light controller in VHDL is used for an intersection between highway and …

VHDL code for debouncing buttons on FPGA

When pressing buttons on FPGA, there are unpredictable bounces which are unwanted. This VHDL code is to debounce buttons on FPGA by only generating a …

How to generate a clock enable signal

This post is about to tell you how to generate a clock enable signal (<i>not gated clocks</i>) to drive another logic using the same clock domain instead of …

Verilog code for Clock divider on FPGA

Last time, I presented a VHDL code for a clock divider on FPGA. This Verilog project provides full Verilog code for the Clock Divider on FPGA …

VHDL Code for Clock Divider on FPGA

This VHDL project presents a full VHDL code for clock divider on FPGA. Testbench VHDL code for clock divider is also provided. The VHDL code for the …

Verilog vs VHDL: Explain by Examples

Last time, I presented in detail what actually FPGA programming is and how to get started with FPGA design. A brief history of Verilog and VHDL was …

What is FPGA Programming?

Last time, I presented in detail what exactly an FPGA is and the advantage of FPGAs over ASICs and microcontrollers. FPGAs are nothing, but …

Altera FPGA boards for beginners

<b>Last time, I presented my four recommended and affordable Xilinx FPGA boards for beginners. The recommended Xilinx FPGA boards offer good enough</b> …

FPGA Projects

This page presents FPGA projects on fpga4student.com. The first FPGA project helps students understand the basics of FPGAs and how Verilog/ VHDL …

FPGA Projects, Verilog Projects, VHDL Projects

[FPGA tutorial] How to interface a mouse with Basys 3 FPGA<p>Last time, I presented an FPGA tutorial on how to control the 4-digit 7-segment display on …

Xilinx FPGA boards for beginners

As a FPGA website for beginners or students, I always look for good and cheap Xilinx FPGA boards for beginners. There are many cheap Xilinx FPGA …

N-bit Adder Design in Verilog

<b>The next Verilog/ VHDL project is a complete co-processor specially designed for cryptographic applications. The co-processor has standard</b> …

Verilog code for Multiplexers

Multiplexers are one of the main combinational logic components in digital circuits. Multiplexers are used for selecting one of many different …

Verilog code for Decoder

Decoder is one of the main combinational components in digital circuits. Decoders are mainly used in memory address decoding and data …

Pipelined MIPS Processor in Verilog (Part-3)

This project is to present the Verilog code for a 32-bit pipelined MIPS Processor. In part 2, I presented all the Verilog code for the single-cycle …

Tic Tac Toe Game in Verilog and LogiSim

<b>Tic Tac Toe is a very popular paper-and-pencil game in a 3x3 grid for two players. The player who makes the first three of their marks in a diagonal,</b> …

How to write Verilog Testbench for bidirectional/ inout ports

This post describes how to write a Verilog testbench for bidirectional or inout ports. This happens in special designs which contain bidirectional or …

Verilog code for debouncing buttons on FPGA

This post is to present a simple debouncing Verilog code for buttons on FPGA.<p>Mechanical switches/ buttons cause the unpredictable bounce in the …

Verilog Code for 16-bit RISC Processor

In this Verilog project, Verilog code for a 16-bit RISC processor is presented.<p>The RISC processor is designed based on its instruction set and …

Verilog code for counter with testbench

In this project, Verilog code for counters with testbench will be presented including up counter, down counter, up-down counter, and random</b> …

Verilog code for Full Adder

In this Verilog project, Verilog code for Full Adder is presented. Both behavioral and structural Verilog code for Full Adder is implemented.<p>Verilog …

Verilog code for D Flip Flop

D Flip-Flop is a fundamental component in digital logic circuits. Verilog code for D Flip Flop is presented in this project. There are two types of D …

Verilog code for a comparator

In this project, a simple 2-bit comparator is designed and implemented in Verilog HDL. Truth table, K-Map and minimized equations for the comparator …