Andrew

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Events

Cross-viewing improves ASIC & FPGA debug efficiency

We introduced the philosophy behind the Blue Pearl Software suite of tools for front-end analysis of ASIC & FPGA designs in a recent post. As we said …

Debugging

Tcl scripts and managing messages in ASIC & FPGA debug

Our previous Blue Pearl post looked at the breadth of contextual visualization capability in the GUI to speed up debug. Two other important aspects …

Debugging

The Value of High Reliability RTL for FPGA Design

Introduction<p>Today’s FPGA designs are typically developed by assembling between 50 to 100 unique IP blocks to form a complete System on Chip (SoC) …

What Makes a Great Verification Methodology

Today’s modern Electronic Design Automation (EDA) tools are built to solve the most challenging of design problems. For IP, FPGA and ASIC design, …

Adam Taylor’s MicroZed Chronicles, Part 227: Blue Pearl Visual Verification Suite automates design checking to improve design quality

Over the last couple of weeks, we have examined how we can debug our designs using Micrium’s μC/Probe (Post 1 and Post 2) or with the JTAG to AXI …

Medical Devices

<b>Medical Device Development and Testing</b><p>Medical device safety and effectiveness plays a critical role in healthcare. The development, delivery, …

Blue Pearl in Japan, Requestor Information

Blue Pearl Software Unveils JumpStart Training and Consulting - Blue Pearl Software Inc.

<i>Personalized JumpStart Services Ensure Out-of-the Box Productivity for ASIC, FPGA and IP RTL Verification</i><p>SANTA CLARA, California – January 24, 2017 – …

Debugging Environment

Eliminate Frustration and Save Time<p>Now you won’t need to use external third party debugging tools such as Verdi3™ to navigate and trace though the …

EDA Software & Systems | Programs for Mobile Phones | Computer & Circuit Design Program

<b>Advanced Technologies for IP and FPGA Verification</b><p>Blue Pearl Software is an electronic design automation (EDA) company that offers a unique and …

Advanced Clock Environment (ACE)

Overview<p>Blue Pearl Software’s ACE offers the capability to visualize clocks and asynchronous clock domain crossings in RTL designs to help users …

Automatic SDC Generation

Overview<p>ASICs and FPGAs have many false paths and multi-cycle paths that implementation tools attempt to optimize to make timing goals. These paths …

Blue Pearl Software’s CDC Analysis Just Got a Whole Lot Faster - Blue Pearl Software Inc.

<i>Announcing Visual Verification Suite 2017.3</i><p>SANTA CLARA, California – Nov 8, 2017 – Blue Pearl Software, Inc., the leading provider of design …

Management Dashboard

Overview<p>Guarantee high reliability RTL with the Visual Verification Suite Management Dashboard.The Blue Pearl Management Dashboard delivers real-time …

Clock Domain Crossing ( CDC )

Overview<p>The Blue Pearl Software Suite offers the capability to analyze ASIC and FPGA designs for Clock Domain Crossing (CDC) issues:<p>– Finds places in …

RTL Analysis – Systems Development Life Cycle ,Design a Program & Compliance

<b>The usability of lint, the power of formal verification</b><p>Blue Pearl Software offers an innovative validation tool that simplifies and speeds up design …

Blue Pearl Software: Path Analysis

Creating and Delivering High Reliability RTL, Case Studies (DAC 2017)

What FPGA Vendor Tools Don’t Say About Your Design (DAC 2017)

Clock Domain Crossing Challenges and Solutions (DAC 2017)